总线接口定时
timing differences───时间性差异
solidity interface───固体界面
communication interface───[通信][计]通信接口
abutment interface───桥台界面
user interface───用户界面
forenoon timing───上午时间
serial interface───串联接口;n.串行接口
timing chain───[仪]定时链
wronging timing───错误的时间
The system utilizes CPLD to realize logical and timing control between DSP and multi-channel ADC. The interface between DSP's HPI and PCI bus is employed to achieve high-speed data transmission.───该系统采用CPLD实现了DSP与多通道adc的逻辑和时序控制,通过DSP的HPI与PCI总线接口设计实现了采集数据的高速传输。
FSM model of target PCI bus interface controller is then provided based on PCI bus operation timing.───根据PCI总线操作时序,提出了从设备接口控制器的有限状态机模型。
- disloyal lover
- dislover
- crown green
- eat the soul
- bus interface unit
- actually not for a long time
- barn light
- both late for school
- barn cook
- actually not happy
- both late sleepers and early
- eat the soup
- eat the sugar
- automated decision system
- cheer for the players
- actually not really
- aqueous tension
- bus interfacing
- day forecast
- automated design system
- both left and right